j7

e-ISSN: 2590-4132

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15th January

15th May

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Honorary Editor

M. Nayfeh (USA)

Editor-in-Chief

Y. Al-Douri

Email: yarub.a@siats.co.uk

Editors

S. Abdullah (Malaysia)

O. Alani (UK)

T. Al Smadi (Jordan)

M. Ameri (Algeria)

N. E. Arif (Iraq)

V. K. Arora (USA)

N. Badi (USA)

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Z. Cai (USA)

A. Chaudhry (India)

N. E. Christensen (Denmark)

D. Chua (Singapore)

H. Ekinci (Turkey)

S. El-Safty (Japan)

Y. P. Feng (Singapore)

L. Feo (Italy)

M. Henni (UK)

D. Hui (USA)

N. N. Jandow (Iraq)

M. R. Johan (Malaysia)

R. Jose (Malaysia)

N.Joshi (USA)

A. H. Jumaa (Iraq)

M. A. R. Khan (USA)

R. Khenata (Algeria)

M-B Leptit (France)

J. Lui (USA)

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A. H. Reshak (Czech Republic)

A. Rubio (Spain)

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P. Schwerdtfeger (New Zealand)

U. Schwingenschloegl (Germany)

T. E. Simos (Greece)

J. Sing (Australia)

P. R. Somani (India)

M. Tanemura (Japan)

N. Tit (UAE)

K. D. Verma (India)

S. Wang (Singapore)

J. Whitaker (USA)

A. Zaoui (France)

D. H. Zhang (Singapore)

Analytical Modeling and Simulation of Advanced Silicon Nanowire Transistors

        Surrounding gate architecture for transistors has been shown to alleviate many of the problems posted by scaling and short channel effects. Semiconducting nanowires have recently attracted considerable attention in the semiconductor industry. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well as for technology. In this paper, we have proposed a new analytical model for three different geometries of Surrounding Gate Silicon Nanowire Transistors. I–V characteristics (current-voltage) of the devices are effectively derived in all the three regions of operation. The variation of threshold voltage and drain current due to the device parameters like silicon thickness, doping concentration and radius are also predicted. Effectiveness of the models are fully validated by comparing the analytical results with the TCAD simulation results.  

 

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