j7

e-ISSN: 2590-4132

Quarterly Issues

15th January

15th May

15th September

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Honorary Editor

M. Nayfeh (USA)

Editor-in-Chief

Y. Al-Douri

Email: yarub.a@siats.co.uk

Editors

S. Abdullah (Malaysia)

O. Alani (UK)

T. Al Smadi (Jordan)

M. Ameri (Algeria)

N. E. Arif (Iraq)

V. K. Arora (USA)

N. Badi (USA)

S. Baroni (Italy)

M. Bounoudina (Bahrain)

Z. Cai (USA)

A. Chaudhry (India)

N. E. Christensen (Denmark)

D. Chua (Singapore)

H. Ekinci (Turkey)

S. El-Safty (Japan)

Y. P. Feng (Singapore)

L. Feo (Italy)

M. Henni (UK)

D. Hui (USA)

N. N. Jandow (Iraq)

M. R. Johan (Malaysia)

R. Jose (Malaysia)

N.Joshi (USA)

A. H. Jumaa (Iraq)

M. A. R. Khan (USA)

R. Khenata (Algeria)

M-B Leptit (France)

J. Lui (USA)

R. Nowak (Finland)

S. Radiman (Malaysia)

M. V. Reddy (Singapore)

A. H. Reshak (Czech Republic)

A. Rubio (Spain)

M. Rusop (Malaysia)

P. Ruterana (France)

P. Schwerdtfeger (New Zealand)

U. Schwingenschloegl (Germany)

T. E. Simos (Greece)

J. Sing (Australia)

P. R. Somani (India)

M. Tanemura (Japan)

N. Tit (UAE)

K. D. Verma (India)

S. Wang (Singapore)

J. Whitaker (USA)

A. Zaoui (France)

D. H. Zhang (Singapore)

Analysis of Reliability for Fault Tolerant Design in NANO CMOS Logic Circuit

The emerging nano scaled electronic devices are Carbon Nanotubes (CNT), Silicon nanowires (SINW), nano CMOS switches etc. In Nano CMOS switches, the devices can be interconnected to build the nano scaled CMOS circuit. In this nano CMOS circuit, faults occur at three levels, such as gate level, circuit level and switch level. This paper focusses on the switch level faults of stuck-open or stuck-off and stuck-short or stuck-on that frequently occurs in CMOS switches. To overcome the switch level faults and to increase the reliability, the fault tolerant technique known as the Quadded Transistor (QT) structure is used. An analytical model has been formulated to determine the probability of failure by analyzing the stuck open and stuck short faults. Also, the model has been formulated by implementing QT structure for the single CMOS NAND2 gate. By the use of analytical formulations, the results has been simulated for the occurrence of minimum to maximum number of defective transistors in CMOS logic circuit.

 

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